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w wm8803 digital audio interface receiver wolfson microelectronics plc w :: www.wolfsonmicro.com product preview, september 2003, rev 1.1 copyright ? 2003 wolfson microelectronics plc description the wm8803 is a digital audio interface receiver conforming to iec 60958/61937 and eiaj cp-1201. it supports input audio data rates up to 192khz and a maximum output data length of 24 bits. the wm8803 has a flexible digital output port that allows the user access to channel status pre-emphasis information, input signal sampling frequency, sub-code q data with the associated crc flags and other status data. the wm8803 can output an externally input clock signal that can be used as an adc converter clock when the pll is unlocked. it also maintains the continuity of the output clock when the clock is switched. the wm8803 includes a built-in oscillator and serial data input circuits and allows the system micro-controller to read the sub-code q data and the channel status. it provides several low-power modes, thus supporting applications that require long battery life, such as portable audio devices and pdas. the device is available in a 24-pin tssop package. features ? pll circuit for synchronization with transferred input bi- phase mark signal. ? input sampling frequency: 32khz to 192khz ? outputs clocks: fs, 64fs, and one of 128fs, 256fs, 384fs, and 512fs. ? 4-wire ccb mpu serial control or hardware default interface ? master clocking mode ? programmable audio data interface modes ? i 2 s, left, right justified ? 16/20/24/32 bit word lengths ? 3.3v digital supply operation ? 5v tolerant digital input ports applications ? dvd receivers ? dvd-r/w players ? audio video receivers ? portable music players block diagram w wm8803 pll microcontroller interface demodulation and lock detection data buffer clock selector fs calculator audio interface amp c & u di cl ce pd audio do e/int ugpi rxin lpf xin xout sdin error clkout bclk lrclk sdato avdd agnd dvdd dgnd
wm8803 product preview w pp rev 1.1 september 2003 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................3 ordering information ..................................................................................3 pin description ................................................................................................4 absolute maximum ratings.........................................................................5 recommended operating conditions .....................................................5 electrical characteristics ......................................................................6 input and output pin capacitance................................................................... 6 dc characteristics............................................................................................... 6 system timing requirements ............................................................................. 7 serial interface timing requirements.......................................................... 7 micro-controller interface timing requirements ................................. 8 device description .........................................................................................9 system reset ( _____ pd )................................................................................................... 9 low power modes ................................................................................................. 9 clocks...................................................................................................................... 11 data input and output ....................................................................................... 17 error output and processing (error)....................................................... 22 channel status data .......................................................................................... 24 user general purpose interface output port ( __________ ugpi )........................... 24 micro-controller interface (e/int, ce, cl, di, do) ...........................28 interrupt output (e/int).................................................................................... 28 ccb addresses ...................................................................................................... 29 data write procedure....................................................................................... 29 data read procedure ........................................................................................ 29 i/o timing .................................................................................................................. 30 write register table ......................................................................................... 31 write data detailed documentation............................................................ 32 read register table ........................................................................................... 37 read data detailed documentation ............................................................. 38 sample application ......................................................................................41 recommended external components ..................................................42 recommended external components values ........................................... 43 package dimensions ....................................................................................44 important notice ..........................................................................................45 address: .................................................................................................................. 45
product preview wm8803 w pp rev 1.1 september 2003 3 pin configuration ordering information device temp. range package wm8803scdt/v -30 to +70 o c 24-pin tssop 16 15 14 13 5 6 7 1 2 3 4 12 11 8 9 10 17 18 19 20 21 22 23 24 xout error pd nc ce cl di do e/int audio ugpi rxin xin sdin sdato lrclk bclk clkout dgnd agnd nc lpf avdd dvdd
wm8803 product preview w pp rev 1.1 september 2003 4 pin description pin name type description 1 xout analogue output oscillation amplifier circuit output pin 2 error digital output pll lock error and data error output pin 3 pd 5 digital input system reset and low power mode control input pin (5v tolerant) 4 nc digital input non connection 5 ce 5 digital input micro-controller interface: chip enable input pin (5v tolerant) 6 cl 5 digital input micro-controller interface: serial clock input pin (5v tolerant) 7 di 5 digital input micro-controller interface: write data input pin (5v tolerant) 8 do digital output micro-controller interface: read data output pin 9 e / int digital output pre-emphasis detection or micro-controller interface interrupt output pin 10 audio digital output channel status bit 1 non-pcm data detection output pin 11 ugpi digital output user general purpose interface output pin 1 12 rxin 5 digital input digital data input pin (5v tolerant) 13 dvdd supply digital system power supply 14 avdd supply analog system power supply 15 lpf analogue output pll loop filter connection pin 16 nc no connection 17 agnd supply analog system ground 18 dgnd supply digital system ground 19 clkout digital output system clock output pin 2 20 bclk digital output 64fs clock output pin 21 lrclk digital output fs clock output pin 3 22 sdato digital output demodulated data output pin 23 sdin digital input serial digital data input pin (5v tolerant) 24 xin digital input oscillation amplifier element connection or external clock input pin notes: 1. micro-controller register output or clock switching transition period signal. 2. 128fs, 256fs, 384fs, 512fs, or oscillator amplifier outputs 3. other than i 2 s mode; low: right channel, high: left channel i 2 s mode; low: left channel, high: right channel 4. i/o voltage handling: i or o pins: ?0.3 to +3.6v, except annotated pins: ?0.3 to +5.5v 5. to prevent logic circuit latch-up, all power supply levels must be applied or removed simultaneously.
product preview wm8803 w pp rev 1.1 september 2003 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operatin g beyond these limits. device functional operating limits and guaranteed performance specifications are given under el e characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically suscept damage from excessive static voltages. proper esd precautions must be taken during handling and storage device. condition symbol conditions min - max maximum supply voltage avdd max 1 ?0.3 to 4.6v maximum supply voltage dvdd max 2 ?0.3 to 4.6v input voltage 1 v in1 3 ?0.3 to vdd + 0.3v input voltage 2 v in2 4 ?0.3 to 5.8v storage temperature t stg ?55 to 125c operating temperature t opg ?30 to 70c maximum output current i i , i o 5 20 ma notes: 1. avdd pin 2. dvdd pin 3. xin pin 4. rxin, sdin, pd, ce, cl, and di pins 5. per single input or output pin recommended operating conditions parameter symbol test conditions min typ max unit supply voltage 1 avdd, dvdd 1 2.7 3.3 3.6 v supply voltage 2 avdd, dvdd 2 3.0 3.3 3.6 v input voltage range 1 v in1 3 0 3.3 3.6 v input voltage range 2 v in2 4 0 3.3 5.5 v operating temperature t opg ?30 ? 70 c notes: 1. pllck [1:0] = ?00? or pllck [1:0] = ?01? 2. pllck [1:0] = ?10? or pllck [1:0] = ?11? 3. xin pin 4. rxin, sdin, pd , ce, cl, and di pins
wm8803 product preview w pp rev 1.1 september 2003 6 electrical characteristics input and output pin capacitance test conditions avdd = dvdd = v in1 = v in2 = 0 v, ta = 25c, f = 1mhz parameter symbol test conditions min typ max unit input and output pin capacitance input pins c in 1 ? ? 10 pf output pins c out 1 ? ? 10 pf notes: 1. avdd = dvdd = v in1 = v in2 = 0 v, ta = 25c, f = 1mhz dc characteristics test conditions ta = 25c, avdd = dvdd = 3.3v, agnd = dgnd = 0v parameter symbol test conditions min typ max unit dc characteristics high-level input voltage v ih 1 0.7dvdd ? ? v low-level input voltage v il 1 ? ? 0.2dvdd v high-level input voltage v ih 2 2.0 ? 5.8 v low-level input voltage v il 2 ?0.3 ? 0.8 v high-level output voltage v oh 3 dvdd ? 0.8 ? ? v low-level output voltage v ol 3 ? ? 0.4 v high-level output voltage v oh 4 dvdd ? 0.8 ? ? v low-level output voltage v ol 4 ? ? 0.4 v high-level output voltage v oh 5 dvdd ? 0.8 ? ? v low-level output voltage v ol 5 ? ? 0.4 v current drain i dd1 6 ? 6.5 13 ma current drain i dd2 7 ? ? 0.1 a current drain i dd3 8 ? 4.5 9 ma current drain i dd4 9 ? 5 10 ma notes: 1. cmos level pins: xin pin 2. ttl level pins: input pins other than those listed above. 3. i oh = ?8ma, i ol = 6ma: clkout pin 4. i oh = ?2ma, i ol = 2ma: bclk, lrclk, sdato, and do pins 5. i oh = ?1ma, i ol = 1ma: output pins other than those listed above. 6. operating mode: pllsel = ?0?, ampopr = ?0?, f s = 44.1khz, c l = 30pf 7. low power mode condition 1) : _____ pd = low 8. low power mode condition 2) pdown [1:0] = ?01?, xin = 11.2896mhz, c l = 30pf 9. low power mode condition 3) : pdown [1:0] = ?10?, xin = 11.2896mhz, c l = 30pf
product preview wm8803 w pp rev 1.1 september 2003 7 system timing requirements test conditions ta = 25c, avdd = dvdd = 3.3v, agnd = dgnd = 0v parameter symbol test conditions min typ max unit system timing information rxin sampling frequency f fs1 1 30 ? 195 khz rxin sampling frequency f fs2 2 30 ? 108 khz xin clock frequency f xf1 3 ? 11.2896 ? mhz xin clock frequency f xf2 4 ? 12.2880 ? mhz xin clock frequency f xf3 5 ? 16.9344 ? mhz xin clock frequency f xf4 6 ? 22.5792 ? mhz xin clock frequency f xf5 7 ? 24.5760 ? mhz xin clock frequency f xf6 8 ? 33.8688 ? mhz clkout clock frequency f mck 2 ? 100 mhz clkout clock jitter t j ? 200 ? ps notes: 1. pllck [1:0] = ?00? 2. settings other than pllck [1:0] = ?00?. 3. xisel [3:0] = ?0000? 4. xisel [3:0] = ?0001? 5. xisel [3:0] = ?0010? 6. xisel [3:0] = ?0100? 7. xisel [3:0] = ?0101? 8. xisel [3:0] = ?0110? serial interface timing requirements clkout bclk sdatao t bdo lrclk ugpi t mbo t tkt figure 1 serial interface timing requirements
wm8803 product preview w pp rev 1.1 september 2003 8 test conditions ta = 25c, avdd = dvdd = 3.3v, agnd = dgnd = 0v parameter symbol test conditions min typ max unit clkout to bclk delay t mbo ? ? 10 ns bclk to sdato delay t bdo ? ? 5 ns ____ ugpi low-level pulse width t tkt 1 ? ? 100 ms notes: 1. when setting the clock switching transition period signal output micro-controller interface timing requirements test conditions ta = -30~70c, avdd = dvdd = 3.3v, agnd = dgnd = 0v parameter symbol test conditions min typ max unit micro-controller interface timing information pd low-level pulse width t pddw 200 ? ? s e/int high-level pulse width t intuw 1 5 1/fs 63 s cl low-level pulse width t cldw 100 ? ? ns cl high-level pulse width t cluw 100 ? ? ns cl to ce setup time t cesetup 50 ? ? ns cl to ce hold time t cehold 50 ? ? ns cl to di setup time t disetup 50 ? ? ns cl to di hold time t dihold 50 ? ? ns cl to ce hold time t clhold 50 ? ? ns cl to do delay time t cltodo ? ? 20 ns ce to do delay time t cetodo ? ? 20 ns notes: 1. intopf = ?1?, intsel = ?1?, and fs is the input sampling frequency. t cluw t intuw cl ce di t cetodo t cltodo e/int do t cldw t disetup t dihold t cesetup t cehold t clhold hi-z figure 2 micro-controller interface timing requirements
product preview wm8803 w pp rev 1.1 september 2003 9 device description system reset ( _____ pd) the system operates normally when pd is set to high level after applying a supply voltage of 2.7v(3.0v) or higher. following power on, the system is reset by setting pd to low level again. system reset is enabled by setting pdb at power on. if a crystal oscillator is used, after setting pd low level and then high level, at least 10ms should be allowed before starting normal operation until the oscillator element is stable. vdd pd system reset system operation 2.7v 2.0v t > 200 sec t figure 3 pd pin levels at power on low power modes the wm8803 not only supports a total system power down mode controlled with the pd pin but also provides low-power modes in which only certain functions operate. these low power modes are controlled by pdown[1:0] . the ?power down? mode controlled by the pd pin applies to all circuits in the wm8803. all clocks are stopped and the registers are initialized. the xin and xout pins continue to operate in the pdown[1:0] controlled low power mode, which stops all circuits other than the oscillator amplifier. the xout signal can be used as the master clock for a dsp or other circuits. the clkout, bclk, lrclk, sdato, sdin, xin and xout pins continue to operate in the pdown[1:0] controlled low power mode, which stops all circuits other than the oscillator amplifier and the divider circuit . this mode can be used to minimize power consumption during analogue data reception. in a low power mode set with the pdown[1:0] and with the oscillator amplifier stopped by setting ampopr , it will not be possible for the wm8803 to provide a clock output. the ampopr overrides all other oscillator settings. note that the pllopr setting is invalid and the pll circuit will be stopped. when a low power mode is set up with the pdown[1:0] , it is possible to write to the micro-controller registers. however, all the sub-code q and channel status data will read out as zeros.
wm8803 product preview w pp rev 1.1 september 2003 10 the low power modes are listed in table 1. mode pdb ampopr pllopr pdown1 pdown0 function (1) l reset (stand-by) (2) 0 0 0 0 normal operation (3) 0 1 0 0 vco stopped. (4) 0 0 1 all circuits except the oscillator amplifier stopped. (5) 0 1 0 all circuits except the oscillator amplifier and divider circuit stopped. (6) 1 0 0 0 oscillator amplifier stopped. (7) h 1 1 all circuits stopped. table 1 low power modes the table below lists the output pin states in the above modes. output pin mode (1) mode (2) mode (3) mode (4) mode (5) mode (6) mode (7) audiob l output l l l output l ugpib h output output output output output output clkout l output output output output output l bclk l output output l output output l or h lrclk l output output l output output l or h sdato l output output l output output l xout h output output output output h h error h output h h h output h e/int l output l l l output l table 2 output pin states in modes (1) to (7) notes: 1. in modes (3), (4), and (5), the clock supplied to xin is used as the source. 2. mode (3) applies in the state where an external clock other than clkout is supplied to xin. if xin and clkout are connected, no clock signals are output in this mode. 3. mode (6) applies when the pll circuit is locked. when the pll circuit is unlocked, all circuits will go to the stopped state since no clock signal is supplied to xin. 4. in mode (7), the states immediately prior to entering mode (7) will be retained.
product preview wm8803 w pp rev 1.1 september 2003 11 clocks pll (lpf) the wm8803 includes a vco (voltage controlled oscillator) that can synchronize with data corresponding to sampling frequencies from 30k to 195khz. the locking frequency is selected by setting pllck[1:0] . the vco circuit can be stopped by setting pllopr . the range of input data that can be received depends upon the settings of the pllck[1:0] . the (512/2)fs entry for the pllck[1:0] = ?11? in table 3 is a state where the pll itself is synchronized with the 512fs clock, but the clock signal output from clkout is a frequency 1/2 that of the pll locked frequency i.e.256fs. this (512/2)fs lock frequency has the same functions as the 256fs setting from clkout and can be convenient for certain applications. refer to the output clocks section for details. it is recommended that the 256fs setting of pllck[1:0] = ?00? is used to reduce the system power consumption, especially in portable equipment. for best performance, it is recommended that the 512fs setting of pllck[1:0] = ?10? or the (512/2)fs of pllck[1:0] = ?11? is used. pllck1 pllck0 pll lock frequency input data reception range 0 0 256fs 30k to 195khz 0 1 384fs 30k to 108khz 1 0 512fs 30k to 108khz 1 1 (512/2)fs 30k to 108khz table 3 input data reception ranges by pll lock frequency setting the lpf is the pll loop filter connection. use capacitor and resistor components of the recommended values as listed in the table below according to the pllck[1:0] settings used. pllck1 pllck0 r0 c0 c1 0 0 0 1 150 ? 0.047f 0.0068f 1 0 1 1 150 ? 0.068f 0.0047f table 4 loop filter component values c 1 c 0 r 0 lpf figure 4 loop filter structure
wm8803 product preview w pp rev 1.1 september 2003 12 oscillator amplifier (xin and xout) the following methods can be used to supply a clock signal to the internal oscillator amplifier. (a) oscillator element clkout xin xout (b) external clock signal clkout xin xout clkout xin xout (c) clkout clock signal figure 5 xin and xout circuit structures if an oscillator element is used, it is recommended that it provides the desired system operating frequency as its fundamental frequency. since the load capacitance depends on the oscillator element characteristics, the circuit must be designed for the crystal used. in normal operation, the clock signal to the xin pin should be supplied at all times. an externally supplied clock is used when the pll circuit is unlocked and when xin is the clock source. a clock source input to xin is also required when calculating the input data sampling frequency. a clock of frequency 11.2896, 12.288, 16.9344, 22.5792, 24.576, or 33.8688mhz that matches the setting of the xisel[2:0] should be applied. digital data should only be input after the xisel[2:0] has been set to match the oscillator or external clock input frequency. the wm8803 may malfunction if data is input when the input frequency and xisel[2:0] frequency do not match. the wm8803 will operate even when the frequency set with the xisel[2:0] and the frequency supplied to xin differ. however, maintenance of continuity of clock switching and the input fs calculation are not guaranteed. the wm8803 supports an application in which clkout is connected to xin and xisel3 is set, thus requiring no oscillator element. however, since only the vco is used as the source clock, when the pll is not in the locked state the vco free-running frequency (10m to 16mhz) will be output from clkout. furthermore, input fs calculation and limitation are not possible with this technique. additionally, since no clock is supplied to the oscillator amplifier circuit when the vco is set to the stopped state, the whole system will go to the stopped state. this function limits settings to pllck[1:0] = ?00?.
product preview wm8803 w pp rev 1.1 september 2003 13 the oscillator amplifier normally stops automatically when the pll is locked, but continuous operation can be set by ampcnt . setting the wm8803 to continuous operation mode makes it possible to calculate the input sampling frequency when the pll is locked. however, since both the oscillator amplifier clock and the pll clock signals will be present, users must determined whether or not this adversely affects audio quality. the oscillator amplifier can be stopped when not required by setting the ampopr . when returning from stopped mode to operating mode the application must maintain its state for at least 10ms until the oscillator stabilizes and normal operation resumes. output clocks (clkout, bclk, lrclk) the clock source for the clock outputs clkout, bclk, and lrclk can be selected from two master clocks: the pll circuit and the xin pin. normally, when the pll circuit is locked master clock is switched to the pll source. when the pll circuit is unlocked, master clock automatically switches to the xin source. the clock source can be forcibly selected by setting ocksel . clock continuity is maintained when the clock source is switched due to the locked/unlocked state of the pll circuit or by setting ocksel . clock switching depends on the pll circuit locked/unlocked state at the time ocksel is set. if the pll source is selected by ocksel when the pll circuit is unlocked, the switch will occur automatically after the pll circuit locks. when vco operation is stopped by setting pllopr , xin becomes the clock source. however, clock continuity cannot be maintained if the stopped state is set with the pllopr while the pll circuit is locked. continuity cannot be maintained when switching from the pll locked state with low power mode set. ocksel 0 1 pll state locked unlocked locked unlocked clock source pll xin xin xin table 5 command settings, pll states, and the clock source either the pll clock or the xin clock is output from clkout. the clkout clock signal is divided to create the signals output from bclk and lrclk. the frequency when the pll circuit is locked is set with the pllck[1:0] . when switching from the 512fs setting, ( pllck[1:0] = ?10?) to the (512/2)fs setting ( pllck[1:0] = ?11?) in the pll locked state, it is possible to maintain clock continuity without losing the pll lock. this is also true when changing the frequency is the opposite direction.. using the procedure shown in figure 6 to switch between 512fs and (512/2)fs, the bclk and lrclk output clock will maintain continuity and allow the clkout output clock frequency to be held within a narrow band.
wm8803 product preview w pp rev 1.1 september 2003 14 512fs set data input (512/2)fs set pllck0 = 1 pllck1 = 1 clkout output 24.576 mhz pllck0 = 0 pllck1 = 1 yes no fs = 96 khz fs = 48 khz lock detection fs calculation figure 6 flowchart for clkout output clock narrow band operation the tables below show the output clocks in xin and pll clock source modes. pllck1 pllck0 xisel1 xisel0 clkout bclk lrclk 0 0 0 0 11.2896mhz 2.8224mhz 44.1khz 0 0 0 1 12.2880mhz 3.0720mhz 48khz 0 0 1 0 16.9344mhz 4.2336mhz 66.15khz 0 1 0 0 11.2896mhz 1.8816mhz 29.4khz 0 1 0 1 12.2880mhz 2.0480mhz 32khz 0 1 1 0 16.9344mhz 2.8224mhz 44.1khz 1 0 0 0 11.2896mhz 2.8224mhz 44.1khz 1 0 0 1 12.2880mhz 3.0720mhz 48khz 1 0 1 0 16.9344mhz 4.2336mhz 66.15khz 1 1 0 0 11.2896mhz 2.8224mhz 44.1khz 1 1 0 1 12.2880mhz 3.0720mhz 48khz 1 1 1 0 16.9344mhz 4.2336mhz 66.15khz table 6 xin clock source mode output clocks note: 1. xisel2 = 0, pll unlocked state or forced setting
product preview wm8803 w pp rev 1.1 september 2003 15 pllck1 pllck0 xisel1 xisel0 clkout bclk lrclk 0 0 0 0 22.5792mhz 5.6448mhz 88.2khz 0 0 0 1 24.5760mhz 6.1440mhz 96khz 0 0 1 0 33.8688mhz 8.4672mhz 132.3khz 0 1 0 0 22.5792mhz 3.7632mhz 58.8khz 0 1 0 1 24.5760mhz 4.0960mhz 64khz 0 1 1 0 33.8688mhz 5.6448mhz 88.2khz 1 0 0 0 22.5792mhz 5.6448mhz 88.2khz 1 0 0 1 24.5760mhz 6.1440mhz 96khz 1 0 1 0 33.8688mhz 8.4672mhz 132.3khz 1 1 0 0 22.5792mhz 5.6448mhz 88.2khz 1 1 0 1 24.5760mhz 6.1440mhz 96khz 1 1 1 0 33.8688mhz 8.4672mhz 132.3khz table 7 xin clock source mode output clocks note: 1. xisel2 = 1, pll unlocked state or forced setting pllck1 pllck0 clkout bclk lrclk 0 0 256 s 64fs fs 0 1 384fs 64fs fs 1 0 512fs 64fs fs 1 1 256fs 64fs fs table 8 pll clock source mode output clocks (pll locked state) the clkout output clock frequency can be set to 1/2 its normal value by mckhfo , regardless of the pll locked/unlocked state. clock switching using mckhfo can also be performed in the pll locked state without losing that locked state, but clock continuity is not maintained. if the audio output format is set to bi-phase data output, the bclk output clock frequency will be doubled to 128fs when the pll circuit is locked. however, when unlocked, the bclk frequencies from table 8 will be output. note that the clock continuity is not maintained when this output format is set. clock system diagram this section presents the relationship between the two master clock types and the switching and clock dividing functions. the items in square brackets near the switch and function blocks are the names of write commands. the lock/unlock switch is switched automatically according to the locked/unlocked state of the pll circuit.
wm8803 product preview w pp rev 1.1 september 2003 16 pll (256fs) (384fs) (512fs) 512/2fs) divider 1/2 divider 1/2 1/3 1/4 1/6 1/8 divider 1/256 1/384 1/512 [pllopr] [pllck0] [pllck1] [ampopr] [ampcnt] [xisel0] [xisel1] [xisel2] [xinset] lock/unlock [ocksel] [mckhfo] clkout bclk lrclk rxin xin xout figure 7 master clock system diagram notes on clock source switching in states where the input fs calculation result is restricted by flimit , if the wm8803 is switched by ocksel from the pll locked state (oscillator amplifier stopped) to the xin source clock state, clock continuity is maintained. however, error will temporarily output a high level indicating an error. this is because the oscillator amplifier will switch to the operating state at the same time as the wm8803 switches to xin source operation, and the input fs calculation will be restarted. the fs calculated value prior to this time will be reset and when that is compared to the newly calculated fs value, the transition will be handled as a change in fs. with these settings, the oscillator amplifier must be set to continuous operation mode by ampcnt so that the clock source can be switched by ocksel while maintaining the error state. note that when switching from the oscillator amplifier stopped state to xin (the clock source while the pll circuit is locked), clocks which use xin as the source will be output only after the oscillator amplifier has started operating. inversely, switching from xin to the pll circuit in the locked state allows clocks to be output immediately. in both cases, clock continuity is maintained. when neither an oscillator element nor an external clock is used, but the clkout clock is supplied to xin. the vco free-running frequency is output from clkout; when the pll is unlocked this frequency will be in the range 10 to 16mhz. clock signals created by dividing clkout are output from bclk and lrclk. however, these bclk and lrclk clocks will differ with the wm8803 sample rate set and will vary with the supply voltage and operating environment. care is required when using the clkout, bclk, and lrclk clocks when the pll circuit is unlocked .
product preview wm8803 w pp rev 1.1 september 2003 17 data input and output bi-phase mark modulated digital data input (rxin) the bi-phase mark modulated digital data is input through the rxin pin. the rxin pin supports ttl levels. this allows a 5v optical reception module to be connected directly. bi-phase mark modulated input data reception range setting the wm8803 can restrict the upper limit of the input data sampling frequency received and only receive input data at selected sampling frequencies. the input frequency is set by selecting flimit = 1 and selecting the required sampling rate with fssel[3:0], table 9. fssel3 fssel2 fssel1 fssel0 input data reception range 0 0 0 0 32khz to 96khz 0 0 0 1 32khz only 0 0 1 0 44.1khz only 0 0 1 1 48khz only 0 1 0 0 88.2khz only 0 1 0 1 96khz only 0 1 1 0 44.1khz or 88.2khz only 0 1 1 1 48khz or 96khz only 1 0 0 0 32khz or 44.1khz or 48khz 1 ?. 1 0 ?.. 1 0 ?.. 1 1 ?.. 1 reserved table 9 input data reception range ( fs4xin = 0) note: the notation 32khz to 96khz means 32k, 44.1k, 48k, 64k, 88.2k, or 96khz. the table above only applies when the input fs calculation mode fs4xin = 0. when fs4xin = 1, fs data at twice the shown values is supported. input data that exceeds the set range is handled as an error, and the xin source clock is output. at this time, the sdato output data is determined by the rdtsel setting. when the pll is following a source with a changing fs, such as a cd player with a variable pitch control, if the oscillator amplifier is stopped with the pll in the locked state the fs calculation is not performed. as a result, an input frequency outside the set range will not result in an error. the oscillator amplifier must be set to continuous operation mode to handle sources such as this. in systems that connect clkout to xin and thus do not require an oscillator element, it is not possible to perform the fs calculation. in this mode the reception range cannot be limited. output data formats: normal mode (sdato) the output format of audio data is set up after recovery. in normal mode the sdato audio data range can be of the input data format only. the output format is set with the ofsel[2:0] . the bclk, lrclk, and sdato synchronize to the rising edge of clkout. sdato is synchronized to the falling edge of bclk and is clocked on the rising edge. after an error is detected and error goes output low, the output data is synchronized with the lrclk edge immediately following the error signal. the error low signal is output for the signal outside the effective bit length of the output data.
wm8803 product preview w pp rev 1.1 september 2003 18 left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 16 to 24 bits 16 to 24 bits figure 8 msb first left-justified data output (ofsel [2:0] = 000) left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bclk 1 bclk 16 to 24 bits 16 to 24 bits figure 9 i 2 s data output (ofsel [2:0] = 001) left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 16,20,24 bits 16,20,24 bits figure 10 msb first right-justified data output (ofsel [2:0] = 010,011, or 100)
product preview wm8803 w pp rev 1.1 september 2003 19 output data formats: special mode (sdato) the output format of the audio data is set up after recovery in special mode the sdato audio data range does not necessarily have to match the input data format. the output format is set with the ofsel[2:0] bit. the bclk, lrclk, and sdato synchronize to the rising edge of clkout. sdato is synchronizes to the falling edge of bclk and is clocked on the rising edge. after an error is detected and error goes output low, the output data is synchronized with the lrclk edge immediately following the error signal. bi-phase data output synchronizes to lrclk and the fs clock of the 128fs clock. however, when the pll is unlocked the bclk changes to the 64fs clock, figure 8. the nrz 28bits data output contains 4 bits validity (v), user data (u), channel status (c), preamble b (indicated by z) and 24bit lsb left justified base audio data. when preamble b is confirmed z-bit outputs high in that frame, figures 9 and 10. a error low signal is output for a signal outside the effective bit length of the nrz data output. sdatao lrclk bclk l-ch r-ch c p lsb lsb msb u vp c msb u vp c figure 11 data output timing ? biphase data output sdatao lrclk bclk lsb -24 bit- lsb -24 bit- 28 bits 28 bits notice: ?z? means preamble ?b? l-ch r-ch msb u vz c msb u vz c figure 12 data output timing ? nrz data i 2 s output
wm8803 product preview w pp rev 1.1 september 2003 20 sdatao lrclk bclk lsb -24 bit- lsb -24 bit- 28 bits 28 bits notice: ?z? means preamble ?b? l-ch r-ch msb u vz c msb u vz c figure 13 data output timing ? nrz data lsb first left-justified output serial audio data input format (sdin) the sdin pin is a serial digital audio data input that can accept 24bit data data from sources such as an a/d converter output. when the data input to the sdin is output from the sdato, a clock signal synchronized with the sdin input data must be output from the bclk and lrclk to produce useable signals. except for the special mode setting, the sdin input must have the same format as the required output data format. left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 16 to 24 bits 16 to 24 bits figure 14 msb first left-justified data input
product preview wm8803 w pp rev 1.1 september 2003 21 left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1 bclk 1 bclk 16 to 24 bits 16 to 24 bits figure 15 i 2 s data input left channel right channel lrclk bclk sdin 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 16,20,24 bits 16,20,24 bits figure 16 msb first right-justified data input output data switching (sdin, sdato) the sdato pin outputs the demodulated data when the pll circuit is locked and the sdin input data when the pll circuit is unlocked. switching between sdin and sdato is performed automatically according to the locked/unlocked state of the pll circuit. when xin is the clock source, input data synchronized with the clkout, bclk, and lrclk clocks as the sdin input data. the sdin input data can be output from sdato by setting rdtsta regardless of the pll circuit locked/unlocked state. in this case, the clkout, bclk, and lrclk clocks will also be switched to the xin clock source. the switch occurs in synchronization with the lrclk edge that follows the setting of the rdtsta . the sdato output data can be forcibly muted by setting rdtmut . the muting processing is started in synchronization with the lrclk edge that follows the setting of the rdtmut . the sdato output can be muted in the pll locked state by setting rdtsel . these settings have the following priority order: rdtsel < rdtsta < rdtmut .
wm8803 product preview w pp rev 1.1 september 2003 22 when xin is set to be the clock source with ocksel , the pll circuit will operate as long as pll operation is not stopped by pdown[1:0] or pllopr . in this mode the state of the pll circuit is always output from the error pin. regardless of the pll state information processed can be read out over the micro-controller interface. error sdatao pll locked state sdin data muted demodulated data muted sdin data ugpi lock unlock unlock ugpi: when the clock switching transition period signal is selected figure 17 sdato output data switching timing chart (when rdtsel is set to ?0?) input data sampling frequency calculation this function calculates the input data sampling frequency using the xin clock. in modes where the oscillator amplifier is automatically stopped due to pll circuit lock, the fs calculation is performed and error indicates the error state. calculation completes at the same time the oscillator amplifier is stopped and the fs value is retained. after calculation is confirmed, the value does not change until the pll circuit goes to the unlocked state. in continuous operation mode, the oscillator amplifier continuously repeats the frequency calculation. even when sampling the input data during which the channel status sampled information does not change within the pll capture range, it will still be possible to read out a calculated result that follows the input data. the calculated result can be read out from ccb address 0xec or output registers do4 to do6. note, however, that when the pll synchronizes with data that corresponds to 32k to 192khz. the fs calculation mode can be selected from two modes; a 32k to 96khz calculation mode and a 64k to 192khz calculation mode and is switched by fs4xin . it is not possible to monitor an fs calculation result for the whole 32k to 192khz range at the same time. in systems that connect clkout to xin and thus do not require an oscillator element, the fs calculation result will always be ?out of range?. error output and processing (error) lock error and data error output the error pin outputs a high level when the pll is in the unlocked state or an error occurs in the transmitted data. pll lock error the pll circuit will go to the unlocked state for input data that does not conform to the bi-phase modulation rules and for input data in which the preamble b, m, and w cannot be detected. the error output goes to the high level when a pll lock error occurs and is held high until data modulation has returned to normal for 15 to 50ms. the rise and fall of the error output is synchronized with lrclk. input data transmission error odd input parity errors are detected from the parity bits in the input data. when input parity errors occur for 9 or more consecutive cycles, the error output goes high. the high level is held until the pll is in a locked state for 15 to 50ms, then error returns low. when 8 or fewer consecutive input parity errors occur, an error will only be output for intervals between sub-frames for errors that occurred only when non-pcm data is recognized by the channel
product preview wm8803 w pp rev 1.1 september 2003 23 status data delimiter bit 1. in this case, the parity error flag used for data recognized as pcm data will not be output. other errors even when error has gone low, the wm8803 always acquires bits 24 to 27 (sampling frequency) of the channel status and compares the current data with that of the previous block. if any differences are found, error is immediately set to the high level and the state is handled as a pll lock error. similarly, when flimit is set to restrict fs input range and the input fs calculation results are reflected in the error flags, fs calculation results are compared continuously. if a disparity occurs in the data, error will immediately go high, and the state will be handled as a pll lock error. error occurrence processing this section describes the data processing performed when an error occurs. when up to 8 consecutive input parity errors occur and if the transmitted data is pcm audio data, the data is replaced with the corresponding left and right channel data from the immediately preceding frame. if the transmitted data is non-pcm data, the error data is output without modification. non-pcm data is based on data that was detected before the input parity error that occurred, and is data for which the channel status bit 1 non-pcm data detection bit is ?1?. the output data is muted when 9 or more consecutive parity errors, or a pll lock error, occur. for the channel status output when a parity error occurs, the data for the previous block is retained. data and detection flags pll lock error input parity error (a) input parity error (b) input parity error (c) sdato output pin l l previous data output input fs calculation l l output output channel status data l l previous data previous data sub-code q data l l output ? table 10 data processing when errors occur notes: 1. input parity error (a): when 9 or more consecutive parity errors occur 2. input parity error (b): when up to 8 consecutive parity errors occur in audio data 3. input parity error (c): when up to 8 consecutive parity errors occur in non-pcm burst data the figure below presents an example of the data processing performed when a parity error occurs. error sdatao r-ch previous data value input data lrclk an error occurs a single time muted after 9 or more consecutive errors l-ch r-ch ?. previous data value r-2 l-2 r-0 l-1 r-0 l-0 l-2 r-2 l-2 r-2 l-2 r-2 l-2 r-2 l-4 r-3 l-3 r-2 l-2 r-1 r-4 l-5 r-5 l-6 r-6 l-7 r-7 l-8 r-8 l-1 figure 18 data processing example following a parity error (when pcm data is received)
wm8803 product preview w pp rev 1.1 september 2003 24 error recovery processing when the preamble b, m, and w are detected, the pll circuit goes to the locked state and data demodulation starts. the sdato output data starts on the first lrclk edge after error goes low. sdatao output starts from the lrck edge immediately following the fall of the error flag error internal clock signal lrclk data 15 ms to 50 ms ok figure 19 data processing at the start of data demodulation channel status data data delimiter bit 1 output ( audio ) audio outputs the channel status bit 1, which indicates whether or not the input bi-phase data is pcm audio data. audio output conditions l pcm audio data (cs bit 1 = low) r non-pcm data (cs bit 1 = high) table 11 audio output emphasis information output (e/int) e/int has a shared function as a micro-controller interface interrupt output or, in the initial settings state, it outputs the presence or absence of emphasis of the input signal. this emphasis has a time constant of 50/15s for use in consumer products or broadcast studios. e/int output conditions l no pre-emphasis r 50/15s pre-emphasis table 12 e/int output user general purpose interface output port ( __________ ugpi ) ugpi is a user-settable output port that supports the following functions. ? micro-controller interface register output ? clock switching transition period signal output gpisel selects between these functions. in the initial settings, the micro-controller interface register gpidat is allocated to this pin. the initial setting of the gpidat register is 1, so a high level will be output from ugpi .
product preview wm8803 w pp rev 1.1 september 2003 25 micro-controller interface register output (optical receiver module power down example) this section describes an example in which ugpi outputs a micro-controller interface register, and how that signal is used as the power supply control signal for an optical receiver module. 1. connect the ugpi output to the optical receiver module power supply control switch. 2. after clearing a reset due to _____ pd , the micro-controller interface register output will be selected as the initial setting for ugpi . as a result, the gpidat set value will be output. 3. after a reset is cleared, the initial value of gpidat = 1, and so ugpi will be output high. the control switch will be in the off state, and data will not be supplied from the optical receiver module. 4. setting gpidat = 0 will activate the optical receiver module supply data. controlling the ugpi output with gpidat will allow current drain to be minimized when the optical receiver module is not used. optical receiver module wm8803 rxin ugpi figure 20 ugpi output example (optical receiver module power supply control) micro-controller interface register output (digital data input switch control signal example) ugpi , when used as a micro-controller interface register output, can be used as a control signal that switches the digital data input. if more than one type of data input is required an input selector circuit and a control signal will be required. it is possible to implement two digital data inputs without having to provide a control signal from the micro-controller by using the ugpi output. note that after a reset is cleared, the initial value of gpidat will be 1, and as a result, ugpi will output a high level.
wm8803 product preview w pp rev 1.1 september 2003 26 wm8803 rxin ugpi sw figure 21 ugpi output usage example (data input switching example) clock switching transition period signal output this section describes operation when ugpi is selected as the clock switching transition period signal. when there are changes to the pll circuit locked/unlocked state, the clock switching transition period signal reports to external circuits the output clock state switching transitions. this signal allows the application to grasp the pll lock state transitions and the timing of changes in the clock signals. gpisel is used to select this function. after setting gpisel , ugpi will initially output a high level. this is followed by output low level pulses when the output clock changes due to changes in the pll circuit locked/unlocked state. in the lock pull-in process, the ugpi falling edge is triggered by the word clock generated by the xin clock after input data is detected and the pll circuit locks, and by ugpi rising with the same timing as error after a fixed period has elapsed. in the process where the pll lock state is lost, the ugpi low level pulse is formed by ugpi falling with the same timing as the pll lock detection signal error and by ugpi rising after a fixed number of counts of the word clock generated from xin.
product preview wm8803 w pp rev 1.1 september 2003 27 error clkout vco clock xtal clock pll lock state rxin (a) during the lock pull-in process 15 ms to 50 ms with the same timing as error after pll lock digital data locked unlocked ugpi error clkout vco clock xtal clock pll lock state rxin (b) during the loss of pll lock with the same timing as error digital data unlocked locked ugpi 64/fs (sec) figure 22 clock switching timing
wm8803 product preview w pp rev 1.1 september 2003 28 micro-controller interface (e/int, ce, cl, di, do) interrupt output (e/int) the e/int pin can be set to function as the micro-controller interface interrupt output using intsel . an interrupt is issued when a change occurs in the pll lock state, the output data information or other aspects of wm8803 operation. the interrupt output function consists of registers for selecting interrupts, the e/int pin to output those state transitions, and the registers that store interrupt related data. the e/int pin normally outputs a low level, but outputs a high level when an interrupt occurs. after outputting a high level, it returns to the low level according to the intopf setting. intopf selects whether the e/int pin holds the high level for a fixed period and then is cleared (returning to the low level), or is cleared at the same time as the output register is read. the interrupts can be selected from the items listed in table 13. more than one of these items can be set to be interrupts at the same by setting the contents of ccb address 0xea. the interrupt signal is issued whenever any one of the interrupt events occurs. e/int output = (selected interrupt 1) + (selected interrupt 2) + ... + (selected interrupt n) no. command description 1 interr output when the state of the error pin changes. 2 intpcm output when the state of the audio pin changes. 3 intemp output when the state of the pre-emphasis information changes. 4 intvfl output when the state of the validity flag changes. 5 intfsc output when the input fs calculation result changes. 6 intcsf output when the first 48 bits of the channel status data is updated. 7 intsqy output when the sub-code q data can be read out. table 13 interrupt event settings when an interrupt event occurs the content of the selected interrupt events is stored in the ccb address 0xeb output registers do1 to do7. the read registers for event items 1 through 4 read out the current state of those events regardless of the e/int output. for event items 5 through 7, the state is stored when the event occurs. to monitor interrupt event item 5 in the pll locked state, the oscillator amplifier must be set to continuous operation mode, since the oscillator amplifier clock is used. when e/int is set to output a high-level pulse when interrupt event occurs, the pulse width for each interrupt event will be between 1/2 fs and 3/2 fs. when the wm8803 is set so that e/int is cleared after the output register is read, the clear operation is performed immediately after output register 0xeb is reset. the data for interrupt events 6 and 7 is updated within the periods shown in table 14, the corresponding read registers should be read as soon as possible after the event is detected. data update interval channel status and preamble b 2ms to 6ms sub-code q data 13.3ms (fs = 44.1khz), 6.65ms (2x speed) table 14 data update intervals (input fs = 32k to 96khz)
product preview wm8803 w pp rev 1.1 september 2003 29 ccb addresses the address locations in table 15 are those used to set the parameters, write data values and to read data values from the wm8803 over the micro-controller interface. the micro-controller interface data format conforms to that of the sanyo-developed ccb serial bus format. however, a three state circuit is adopted for the data output instead of the open drain circuit used in ccb. data is input or output after input of the ccb address. see the i/o timing chart for details on the data input and output timing. register content r/w ccb address b0 b1 b2 b3 a0 a1 a2 a3 function settings data 1 write 0xe8 0 0 0 1 0 1 1 1 function settings data 2 write 0xe9 1 0 0 1 0 1 1 1 function settings data 3 write 0xea 0 1 0 1 0 1 1 1 interrupt data output read 0xeb 1 1 0 1 0 1 1 1 fs value, cs data output read 0xec 0 0 1 1 0 1 1 1 sub-code q data output read 0xed 1 0 1 1 0 1 1 1 table 15 register i/o content and ccb addresses data write procedure the data input bit length is 16 bits. after inputting data to one of the ccb addresses 0xe8 to 0xea, set ce to the high level. input data is acquired on the rising edge of cl. the bits marked ?0? in the table are reserved bits. a value of 0 must be written to these bits. data read procedure read data is output from do and goes to the high-impedance state when ce is low. output starts on the ce rising edge following the establishment of the output address by the ccb command on the di pin. after operation the do pin is returned to the high-impedance state by setting ce low. the number of data bits read out differs with the type of data read. interrupt data has 8bits, the channel status related data (0xec) has 56bits, and the sub-code q data (0xed) has 88bits. however, it is not necessary to read out all the data. during readout it is possible to read data up to the point when the cl clock is stopped and the ce pin is set low. for example, when reading the sub-code q data, if the crc flags are read and the data is seen to be corrupted, there is no need to read the data following.
wm8803 product preview w pp rev 1.1 september 2003 30 i/o timing b0 di0 ?. a3 a2 a1 a0 b3 b2 b1 di15 di5 di4 di3 di2 di1 di do hi-z cl ce figure 23 input timing chart (normal, low clock) b0 di0 ?. a3 a2 a1 a0 b3 b2 b1 di15 di5 di4 di3 di2 di1 di do hi-z cl ce figure 24 input timing chart (normal, high clock) b0 a3 a2 a1 a0 b3 b2 b1 di do hi-z cl ce ?. do4 do3 do2 do1 do0 don ?. figure 25 output timing chart (normal, low clock)
product preview wm8803 w pp rev 1.1 september 2003 31 b0 a3 a2 a1 a0 b3 b2 b1 di do hi-z cl ce ?. don ?. ?. do4 do3 do2 do1 do0 figure 26 output timing chart (normal, high clock) note: 1. it is necessary to read do0 with a separate port from di. write register table the table below lists the write registers. input register 0xe8 0xe9 0xea di0 sysrst gpisel intopf di1 0 gpidat 0 di2 pdown0 flimit 0 di3 pdown1 fs4xin 0 di4 pllopr fssel0 0 di5 pllck0 fssel1 0 di6 pllck1 fssel2 0 di7 mckhfo fssel3 0 di8 0 ofsel0 intsel di9 ampopr ofsel1 interr di10 ampcnt ofsel2 intpcm di11 ocksel 0 intemp di12 xisel0 rdtsel intvfl di13 xisel1 rdtsta intfsc di14 xisel2 rdtmut intcsf di15 xisel3 0 intsqy table 16 list of write registers the shaded areas are reserved bits. only a value of 0 may be written to these bits.
wm8803 product preview w pp rev 1.1 september 2003 32 write data detailed documentation di7 di6 di5 di4 di3 di2 di1 di0 mckhfo pllck1 pllck0 pllopr pdown1 pdown0 0 sysrst di15 di14 di13 di12 di11 di10 di9 di8 xisel3 xisel2 xisel1 xisel0 ocksel ampcnt ampopr 0 table 17 input register function settings 1: system settings (0xe8) sysrst: system reset 0: no reset performed (initial value) 1: reset all circuits other than the command registers. pdown[1:0]: low power mode settings (allows the operation of specific functions only) 00: normal operation (initial value) 01: only the oscillator amplifier operates. 10: only the oscillator amplifier and the output clock divider operate. 11: reserved pllopr: pll (vco) operate/stop setting 0: operate (initial value) 1: stop pllck[1:0]: pll locked state clock frequency setting 00: 256fs (initial value) 01: 384fs 10: 512fs 11: (512/2)fs = 256fs mckhfo: clkout output clock frequency setting 0: 1/1 output (initial value) 1: 1/2 output in the pll locked state when switching from the 512fs setting with the pllck[1:0] = ?10? to the (512/2)fs setting with the pllck[1:0] = ?11? it is possible to maintain clock continuity without entering the pll lock error state..this is also the case when switching in the reverse direction. for systems such as portable equipment power consumption can be minimized,by setting pllck[1:0] = ?00? (256fs). systems such as av amplifiers that required best performance, the pllck[1:0] = ?10? (512fs) or the pllck[1:0] = ?11? (512/2fs) setting is recommended.
product preview wm8803 w pp rev 1.1 september 2003 33 ampopr: oscillator amplifier operate/stop setting 0: operate (initial value) 1: stop ampcnt: oscillator amplifier state setting 0: automatically stop in the pll locked state (initial value) 1: always operate ocksel: clock source setting 0: use the xin clock as the source when the pll is unlocked (initial value) 1: use the xin clock as the source regardless of the pll state. xisel[3:0]: xin input frequency setting 0000: 11.2896mhz (initial value) 0001: 12.288mhz 0010: 16.9344mhz 0011: reserved 0001: 22.5792mhz 0010: 24.576mhz 0010: 33.8688mhz 0011: reserved 1xxx: setting used when the clkout pin and the xin pin are connected.
wm8803 product preview w pp rev 1.1 september 2003 34 di7 di6 di5 di4 di3 di2 di1 di0 fssel3 fssel2 fssel1 fssel0 fs4xin flimit gpidat gpisel di15 di14 di13 di12 di11 di10 di9 di8 0 rdtmut rdtsta rdtsel 0 ofsel2 ofsel1 ofsel1 table 18 input register function settings 1: i/o data settings (0xe9) gpisel: ugpi pin setting 0: outputs the micro-controller interface register state. (initial value) 1: outputs the clock switching transition period signal. gpidat: ugpi pin setting (only valid when register output mode is set up) 0: outputs the low level. 1: outputs the high level. (initial value) flimit: input data reception limitation setting 0: no reception limitation. all data within the pll locking range can be received. (initial value) 1: reception is limited. the input fs calculation result is reflected in the error flag according to the fssel[3:0] setting. fs4xin: input fs calculation range setting 0: perform fs calculation for input data in the range 32k to 96 khz. (initial value) 1: perform fs calculation for input data in the range 64k to 192 khz. fssel[3:0]: input data reception range setting (when flimit = ?1? and fs4xin = ?0?) 0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96khz (initial value) 0001: 32khz only 0010: 44.1khz only 0011: 48khz 0100: 88.2khz only 0101: 96khz only 0110: 44.1k or 88.2khz only 0111: 48k or 96khz only 1000: 32k or 44.1k or 48khz 1001-1111:reserved
product preview wm8803 w pp rev 1.1 september 2003 35 fssel[3:0]: input data reception range setting (when flimit = ?1? and fs4xin = ?1?) 0000: 64k, 88.2k, 96k 128k, 176.4k, or 192khz (initial value) 0001: 64khz only 0010: 88.2khz only 0011: 96khz only 0100: 176.4khz only 0101: 192khz only 0110: 88.2k or 176.4khz only 0111: 96k or 192khz only 1000: 64k or 88.2k or 96khz only 1001-1111: reserved ofsel[2:0]: serial audio data output format setting 000: 24-bit msb first left-justified data output (initial value) 001: 24-bit i 2 s data output 010: 24-bit msb first right-justified data output 011: 20-bit msb first right-justified data output 100: 16-bit msb first right-justified data output 101-100: reserved 101: bi-phase data output 110: 28-bit i 2 s data output (nrz data output) 111: 28-bit lsb first left-justified data output (nrz data output) rdtsel: sdato output setting in the pll unlocked state 0: output the sdin data in the pll unlocked state. (initial value) 1: mute the output in the pll unlocked state. rdtsta: sdato output setting 0: observe the rdtsel setting. (initial value) 1: output the sdin data regardless of the pll state. rdtmut: sdato mute setting 0: output the data selected by rdtsel . (initial value) 1: mute the output.
wm8803 product preview w pp rev 1.1 september 2003 36 di7 di6 di5 di4 di3 di2 di1 di0 0 0 0 0 0 0 0 intopf di15 di14 di13 di12 di11 di10 di9 di8 intqsy intcsf intfsc intvfl intemp intpcm interr intsel table 19 input register function settings 1: interrupt settings (0xea) intopf: e/int output setting (only valid when the interrupt output function is selected.) 0: output a high level when an interrupt occurs. (initial value) 1: output a high level pulse when an interrupt occurs. intsel: e/int pin setting 0: output the channel status emphasis information. (initial value) 1: output the micro-controller interface interrupt signal. interr: error signal output setting 0: do not output this signal. (initial value) 1: output changes to the error pin state. intpcm : audio signal output setting 0: do not output this signal. (initial value) 1: output changes to the audio pin state. intemp: channel status emphasis detection flag output setting 0: do not output this flag. (initial value) 1: output the emphasis detection flag. intvfl : parity flag detection flag output setting 0: do not output this flag. (initial value) 1: output the parity flag. intfsc: pll lock frequency calculation result update flag output setting 0: do not output this flag. (initial value) 1: output the pll lock frequency calculation result update flag. intcsf: first 48 bits of channel status data update flag output setting 0: do not output this flag. (initial value) 1: output the first 48 bits of channel status data update flag. intqsy: sub-code q data readout load signal detection flag output setting 0: do not output this flag. (initial value) 1: output the flag that indicates updates to the 80 bits of sub-code q data including the crc.
product preview wm8803 w pp rev 1.1 september 2003 37 if e/int is set up for high level output when an interrupts are generated with intopf , the high-level state will be maintained until the interrupt event output (address 0xeb) is read out. when that data has been read, the e/int output will return to the normal low level. the channel status update flag is computed by comparing the current data with the first 48bits of the previous block, and determining the channel status to have been updated if the data is the same. read register table the table below lists the read registers. output register 0xeb 0xec 0xed do0 0 0 crc do1 outerr outerr crc do2 outpcm outpcm 0 do3 outemp 0 0 do4 outvfl fscal0 0 do5 outfsc fscal1 0 do6 outcsf fscal2 0 do7 outsqy 0 0 do8 0 bit 0 control do9 0 bit 1 control do10 0 bit 2 control do11 0 bit 3 control do12 0 bit 4 address do13 0 bit 5 address do14 0 bit 6 address do15 0 bit 7 address do16 0 bit 8 track do17 0 bit 9 track do18 0 bit 10 track do19 0 bit 11 track do20 0 bit 12 track do21 0 bit 13 track do22 0 bit 14 track do23 0 bit 15 track do24 0 bit 16 index ?.. 0 ?.. ?.. do54 0 bit 46 frame do55 0 bit 47 frame do56 0 0 zero ?.. 0 0 ?.. do86 0 0 abs frame do87 0 0 abs frame table 20 list of read registers
wm8803 product preview w pp rev 1.1 september 2003 38 read data detailed documentation do7 do6 do5 do4 do3 do2 do1 do0 outsqy outcsf outfsc outvfl outemp outpcm outerr 0 table 21 output register: interrupt data output (0xeb) outerr: error output (outputs the state when read) 0: no transmission error and the pll circuit is in the pll locked state. 1: either a transmission error occurred or the pll circuit is in the unlocked state. outpcm: audio output (outputs the state when read) 0: non-pcm signal not detected. 1: non-pcm signal detected. outemp: channel status emphasis detection (outputs the state when read) 0: no pre-emphasis. 1: 50/15s pre-emphasis was applied. outvfl: parity flag detection (outputs the state when read) 0: no error. 1: parity error detected. outfsc: input fs calculation result (cleared after read) 0: no input fs calculation result update. 1: the fs calculation result was updated. outcsf: first 48 bits of the channel status update result (cleared after read) 0: this data was not updated. 1: the data has been updated. outqsy: sub-code q data readout load signal detection (cleared after read) 0: not detected. 1: detected.
product preview wm8803 w pp rev 1.1 september 2003 39 do7 do6 do5 do4 do3 do2 do1 do0 0 0 fscal2 fscal1 fscal0 0 outpcm outerr 0 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 32 bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 40 bit 39 bit 38 bit 37 bit 36 bit 35 bit 34 bit 33 bit 32 48 bit 47 bit 46 bit 45 bit 44 bit 43 bit 42 bit 41 bit 40 table 22 output register: input fs calculation result and channel status data (0xec) error information, non-pcm information, input fs calculation result, and channel status data can be read from this register. note that the error information and the non-pcm data information are the same as those read from 0xeb. outerr: error output (outputs the state when read) 0: no transmission error and the pll circuit is in the pll locked state 1: either a transmission error occurred or the pll circuit is in the unlocked state. outpcm: audio output (outputs the state when read) 0: non-pcm signal not detected. 1: non-pcm signal detected. the input data fs calculation result is allocated as shown in table 23. the target calculation frequencies differ depending on the fs4xin setting. the calculation range differs slightly depending on the xin clock frequency. fs4xin = 0 fs4xin = 1 fscal2 fscal1 fscal0 target fs calculated range target fs calculated range 0 0 0 out of range ? out of range ? 0 0 1 32khz 30.9k to 33.2khz 64khz 62.0k to 66.4khz 0 1 0 44.1khz 42.5k to 45.8khz 88.2khz 85.5k to 91.0khz 0 1 1 48khz 46.3k to 49.9khz 96khz 92.6k to 99.0khz 1 0 0 64khz 62.1k to 66.4khz 128khz 124.0k to 132.8khz 1 0 1 88.2khz 85.6k to 91.0khz 176.4khz 171.0k to 182.2khz 1 1 0 96khz 92.6k to 99.0khz 192khz 185.1k to 198.0khz 1 1 1 ? ? ? ? table 23 input fs calculation result (ta = 25c, vdd = 3.3v, xin = 11.2896mhz) the channel status reads out the first 48bits of the data. since the channel status consists of 192 frames, updated data can always be read out by reading with a period 192 times the period of the input sampling frequency. the processing load on the micro-controller can be reduced by setting the e/int pin to interrupt the output and using the update flag interrupt to read out the data. this flag is output when a comparison of the first 48bits of the current data and the data for the previous block indicates that they are the same.
wm8803 product preview w pp rev 1.1 september 2003 40 do7 do6 do5 do4 do3 do2 do1 do0 0 0 0 0 0 0 0 crc crc 8 address address address address control control control control 16 track track track track track track track track 24 index index index index index index index index 32 minute minute minute minute minute minute minute minute 40 second second second second second second second second 48 frame frame frame frame frame frame frame frame 56 zero zero zero zero zero zero zero zero 64 abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 72 abs second abs second abs second abs second abs second abs second abs second abs second 80 abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame table 24 output register: sub-code q data with crc flags output (0xed) the cyclic redundancy code (crc) is a set of flags that indicates the correctness of the 80bits of sub-code q data. note that the same data is output for both the do0 and do1 crc flags. when sub-code q data is included in the input data, the result of the crc calculation can be read out along with the data. to read out the sub-code q data, the data must be read out with intqsy set as the e/int interrupt output function, and the ic must be set up to output the load signal. when sub-code q data is detected, the e/int signal will output a high level or a high-level pulse. the sub-code q data is updated on each rising edge on the e/int signal. applications must complete readout of this data within 13.3ms (standard speed) or 6.6ms (2 speed) of the rising edge of the e/int signal. crc output conditions l errors were found in the sub-code q data. h the sub-code q data is correct. table 25 crc flag output
product preview wm8803 w pp rev 1.1 september 2003 41 sample application the power supply pin de-coupling capacitors (0.1f and 10f) should be located as close as possible to the wm8803. use ceramic and good quality electrolytic capacitors respectively, with good high-frequency characteristics for these components. use a capacitor with a minimal thermal coefficient for the pll loop filter capacitor. there are no constraints on the nc pin levels. ic operation will not be affected by leaving them open or by holding them fixed at particular levels.
wm8803 product preview w pp rev 1.1 september 2003 42 recommended external components xout error sdatao xin avdd notes: 1. agnd and dgnd should be connected as close to the wm8803 as possible. 2. c 2 , c 3 , c 4, and c 5 should be positioned as close to the wm8803 as possible. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. sdin lrclk clkout bclk agnd dgnd audio interface lpf nc do e/int audio rxin pd cl di nc ce dvdd wm8803cdt cpu interface 1 2 10 9 8 7 6 5 4 3 11 12 ugpi 24 19 20 21 22 23 17 15 13 14 18 16 c 0 r 1 r 2 r 0 r 3 r 4 c 1 c 1 c 2 r 5 avdd dvdd agnd agnd c 5 c 4 + c 5 c 3 + c 4
product preview wm8803 w pp rev 1.1 september 2003 43 recommended external components values component reference suggested value use notes r0 50 to 1k ? ? r1 75 ? coaxial terminator r2 50k to 100k ? input amplifier feedback r3 1m ? oscillator amplifier feedback r4 150 to 330 ? oscillator amplifier current limited r5 * pll loop filter tolerance: 5% c0 0.01 to 0.1f ac coupling c1 1p to 33pf oscillator element load np0 special ceramic capacitor c2 * pll loop filter film capacitor c3 * pll loop filter ceramic capacitor c4 over 1f power supply de-coupling electrolytic capacitor c5 0.1f power supply de-coupling ceramic capacitor table 26 recommended component values note: * refer table 4
wm8803 product preview w pp rev 1.1 september 2003 44 package dimensions d notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. dm031.b dt: 24 pin tssop (6.5 x 6.4 x 1.0 mm) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.03 0.18 a 2 1.00 b 0.17 0.22 0.32 c 0.10 0.15 0.25 d 6.4 6.50 6.95 e 0.50 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.30 0.50 0.70 0 o ----- c l gauge plane 13 24 e b 12 1 e1 e a a2 a1 seating plane -c- 0.1 c 0.08 6.15 6.65 10 o
product preview wm8803 w pp rev 1.1 september 2003 45 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, tha t information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the ti me of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wm?s standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perfo rm when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant inju ry to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual proper ty right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wm?s publication of information regarding any third party?s products or services does not constitute wm?s approval, license, warrant y or endorsement thereof. reproduction of information from the wm web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this informati on with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business prac tice, and wm is not responsible nor liable for any such use. resale of wm?s products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive busin ess practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qw tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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